1. Field of the Invention
The present invention relates to clock generation and, more particularly, to stable clock generation internal to a functional integrated circuit chip.
2. Description of the Related Art
Conventionally, clock generator chips have been separate integrated circuit chips provided to produce clocks of varying frequencies for use by other parts, namely, other integrated circuit chips, of an electrical circuit design. As an example, it is common for a computer system to include a separate clock generator chip to produce the various clocks of different frequencies used by the other circuitry within the computer system. Generally speaking, a clock generator chip will receive an input clock and produce a series of output clocks, each having a different frequency. The output clocks can have frequencies greater than or less than the frequency of the input clock.
FIG. 1 is a block diagram of a representative conventional clock generator chip 100. The clock generator chip 100 includes a multiplier 102 that receives an input clock. The multiplier 102 multiplies the input clock to a greater frequency and supplies the resulting clock to a series of dividers. Specifically, the clock generator chip 100 includes a divider 104 and a phase-lock loop (PLL) 106 which together produce a first clock signal (CLK1). The divider 104 receives the resulting clock from the multiplier 102 and supplies it to the PLL 106 which outputs the first clock (CLK1). The clock generator chip 100 also includes a divider 108 and a PLL 110 that produce a second clock (CLK2) in a similar manner. Further, the clock generator chip 100 includes a divider 112 and a PLL 114 that together produce a third clock (CLK3) also in a similar manner.
When the conventional clock generator chip 100 together with an external clock generator that produces the input clock are powered-on, the clock generator chip 100 is normally held in reset until the input clock has stabilized and propagated through the clock generator chip. Thereafter, the clock generator chip 100 can be released from reset such that the output clocks are able to be produced in a stable manner.
However, more recently, with the ever-increasing integration of functionality onto integrated circuit chips, the clock generator circuitry, including the PLLs, has been moved inside a functional chip. In such situations, there arise stability problems, or unstable conditions, which prevent the reliable generation of the desired clock signals. These unstable conditions can cause the PLLs to incorrectly lock to an unstable external clock if the external clock is powered-up before the functional chip is powered-up. Here, the external clock might not be able to stabilize with the functional chip being powered-off. Hence, when the functional chip is subsequently powered-up, the PLLs within the functional chip may incorrectly lock to the unstable external clock source. Also, if an input to the functional chip is driven while the functional chip is powered down, then the functional chip may experience destructive latch-up when it is subsequently powered up. Still further, if the external clock and the functional chip are powered-up at the same time but the PLLs within the functional chip are disabled while the chip is held in reset, no clocks are propagated through the logic of the functional chip held in reset, so the functional chip will not be properly reset. Also, when the PLLs are eventually enabled, they will drive the functional chip with the unstable clocks until the internal PLLs stabilize.
Thus, there is a need to provide improved techniques for powering on functional chips which include PLL-based clock generation circuitry.
Broadly speaking, the invention relates to stable clock generation within a functional integrated circuit. The functional integrated circuit provides a function other than clock generation, such as peripheral or interrupt control. Typically, the clock generation is phase-lock loop (PLL) based. The functional integrated circuit also typically provides power savings modes to conserve power consumption.
The invention can be implemented in numerous ways, including as a system, a device, an apparatus, and a method. Several embodiments of the invention are summarized below.
As an integrated circuit chip having internal functional circuitry, with the integrated circuit chip receiving an external clock, a reset signal and a clock stop signal, one embodiment of the invention includes: a clock control circuit that receives the reset signal and the clock stop signal and produces a clock control signal; a phase lock loop circuit that receives the external clock and produces a generated clock based on the external clock; a multiplexer that receives the external clock and the generated clock, and outputs at an output terminal one of the external clock and the generated clock as a selected clock based on the clock control signal; and a clock stopper to permit or block passage of the selected clock to the internal functional circuitry of the integrated circuit chip.
As a controller integrated circuit chip for providing control functions for a computer system, one embodiment of the invention includes an on-board clock generation circuit that produces a plurality of clocks, and functional controller circuitry that operates using the plurality of clocks. The on-board clock generation circuit includes at least: a phase lock loop circuit that receives the external clock and produces a generated clock based on the external clock; a multiplexer that receives the external clock and the generated clock, and outputs one of the external clock and the generated clock as a selected clock; and a clock stopper that operates to permit or block passage of the selected clock to the functional controller circuitry of the controller integrated circuit chip.
As a controller integrated circuit chip for providing control functions for a computer system, another embodiment of the invention includes an onboard clock generation circuit that produces a plurality of clocks, and functional controller circuitry that operates using the plurality of clocks. The on-board clock generation circuit includes at least: a phase lock loop circuit that receives the external clock and produces a generated clock based on the external clock; a clock stopper that operates to permit or block passage of either the external clock or the generated clock to the functional controller circuitry of the controller integrated circuit chip. The on-board clock generation circuit also having a run mode and a low-power mode, in the run mode the internal clock is supplied to the functional controller circuitry, and in the low-power mode the clock stopper prevents either the external clock or the generated clock from being supplied to the functional controller circuitry.
As a computer system, one embodiment of the invention includes: a memory device that stores computer code; a microprocessor chip that executes the computer code; a peripheral bus; and a controller chip for the peripheral bus. The controller chip includes an on-board clock generation circuit that produces a plurality of clocks, and functional controller circuitry that operates using the plurality of clocks to control interaction with the peripheral bus. Further, the on-board clock generation circuit includes at least: a phase lock loop circuit that receives the external clock and produces a generated clock based on the external clock; a multiplexer that receives the external clock and the generated clock, and outputs one of the external clock and the generated clock as a selected clock; and a clock stopper that operates to permit or block passage of the selected clock to the functional controller circuitry of the controller chip.
As a method for powering up an integrated circuit chip having functional circuitry and internal clock generation circuitry including phase-locked loops (PLLs) to produce internal clocks, one embodiment of the invention includes the acts of: providing power to the integrated circuit chip and to an external clock source but not providing power to the PLLs; bypassing the PLLs to produce an externally generated clock, the externally generated clock being provided by the external clock source; permitting the externally generated clock to be supplied to the functional circuitry, thereby allowing processing of a reset operation while the PLLs are not producing the internal clocks; subsequently stopping the externally generated clock from being supplied to the functional circuitry after the reset operation is processed; providing power to the PLLs; unbypassing the PLLs after their output are stable; and thereafter permitting the internal clocks produced by the PLLs to be supplied to the functional circuitry, so as to operate the functional circuitry in a normal manner.
The advantages of the invention are numerous. Different embodiments or implementations may have one or more of the following advantages. One advantage of the invention is that stable clock generation with power management can be performed internal to a functional integrated circuit. Another advantage of the invention is that functional integrated circuits are able to be properly reset upon being initially powered-up. Yet another advantage of the invention is that phase-lock loops (PLLs) used in the clock generation lock to desired frequencies in a stable manner. Still another advantage of the invention is that PLLs and clocks can be started and stopped cleanly and in the proper sequence, without having to reset the logic associated with those clocks, for power management.